1. Field of the Invention
The present invention relates to a device for selecting interrupt requests in a microprocessor, and more particularly to a device for selecting the highest priority interrupt request and controlling the application of the request to a RISC-based microprocessor.
2. Discussion of the Background
One type of microprocessor that is currently being used with great success is a RISC-based microprocessor. In this type of architecture, a reduced instruction set is used so that chip complexity is reduced. In these types of devices, software routines perform complex instructions that were previously done in hardware by computers that used more complex instruction sets. As a result, the microcode layer and associated overhead has been eliminated. This type of system is faster and more economical than those using more complex instructions.
One such system is described in the ARM7TDMI datasheet issued August 1995, which is hereby incorporated by reference. This system has been developed by Advanced RISC Machines, Ltd. In this system, eight exceptions are available. These include two interrupts, the FIQ (fast interrupt request) and the IRQ (interrupt request), the prefetch abort, the data abort, the reset, the software interrupt, the undefined instruction, and the branch with link. Thus, two of the exceptions are used as interrupts.
Since it is possible to have more than one of each type of interrupt request, so that it is necessary to select which interrupt should be given priority. In current systems a selecting circuit is used to prioritize the interrupt requests. An interrupt service routine polls the status of the two types of interrupts to determine which request should be served. However, if there are many interrupt requests, and they occur frequently, it takes considerable CPU time to poll the various requests. Accordingly, it is desirable to find a system which reduces the necessary CPU time to establish priority.
Accordingly, the present invention provides a method for prioritizing interrupt requests in a RISC microprocessor.
The present invention further provides an apparatus for prioritizing interrupt requests in a RISC microprocessor.
The present invention also provides a system utilizing hardware to prioritize interrupt requests in a RISC microprocessor.
The present invention still further provides a system for prioritizing interrupt requests utilizing a branch instruction based on a vector using a RISC microprocessor.
The present invention still further provides a system for prioritizing interrupt requests in a RISC microprocessor, which implements an acknowledge vector as a register.
The present invention further provides a system for prioritizing interrupt requests utilizing separate arbitrators for two different types of interrupts.
Briefly, this is achieved by providing a selector and control device which receives interrupt requests with two outputs for the two types of requests connected to corresponding arbitrators. An address from an interrupt vector is selected based on priority and a corresponding signal is sent to the CPU.